Digital System Design
The truth table for an S-R flip-flop has how many VALID entries? A. 3 B. 1 C. 2 D. 4 Answer: A What is one disadvantage of an S-R flip-flop? A. It has no clock input B. It has no Enable input C. It has Race Condition D. It has only a single output. Answer: C How is a J-K flip-flop made to toggle? A.J = 0, K = 0 B.J = 1, K = 0 C.J = 0, K = 1 D.J = 1, K = 1 Answer: D Which of the following is correct for a positive level triggered D flip-flop? A. The output toggles if one of the inputs is held HIGH. B. Only one of the inputs can be HIGH at a time. C. The output complement follows the input when enabled. D. Q output follows the input D when the clock is HIGH. Answer: D What does the triangle on the clock input of a J-K flip-flop mean? A. Level enabled B. Edge-triggered C. Both Level & Edge triggered D. None of All. Answer: B A comparison between ring and johnson counters indicates that: A. A ring counter has fewer flip-flops but requires more decod...