Digital System Design

The truth table for an S-R flip-flop has how many VALID entries?
A. 3
B. 1
C. 2
D. 4
Answer: A

What is one disadvantage of an S-R flip-flop?
A. It has no clock input
B. It has no Enable input
C. It has Race Condition
D. It has only a single output.
Answer: C

How is a J-K flip-flop made to toggle?
A.J = 0, K = 0
B.J = 1, K = 0
C.J = 0, K = 1
D.J = 1, K = 1
Answer: D

Which of the following is correct for a positive level triggered D flip-flop?
A. The output toggles if one of the inputs is held HIGH.
B. Only one of the inputs can be HIGH at a time.
C. The output complement follows the input when enabled.
D. Q output follows the input D when the clock is HIGH.
Answer: D

What does the triangle on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Edge-triggered
C. Both Level & Edge triggered
D. None of All.
Answer: B

A comparison between ring and johnson counters indicates that:
A. A ring counter has fewer flip-flops but requires more decoding circuitry
B. A ring counter has an inverted feedback path
C. A johnson counter has more flip-flops but less decoding circuitry
D. A johnson counter has an inverted feedback path
Answer: D

What is meant by parallel-loading the register?
A. Shifting the data in all flip-flops simultaneously
B. Loading data in two of the flip-flops
C. Loading data in all four flip-flops at the same time
D. Momentarily disabling the synchronous SET and RESET inputs
Answer: C

Counter is a
A. Combinational Circuit
B. Sequential Circuit
C. Combinational & Sequential both
D. None of the above
Answer: B

The system having memory elements are called
A.combinational circuits
B.Sequential circuits
C.logic circuits
D.complex circuits
Answer: B

To operate correctly, starting a ring counter requires:
A. Clearing all the flip-flops
B. Presetting one flip-flop and clearing all the others
C. Clearing one flip-flop and presetting all the others
D. Presetting all the flip-flops
Answer: B

Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
A. Input clock pulses are not used to activate any of the counter stages.
B. Input clock pulses are applied only to the last stage
C. Input clock pulses are applied only to the first and last stages
D. Input clock pulses are applied simultaneously to each stage
Answer: D

The dont care condition in a table is represented by
A. a
B. b
C. c
D. x
Answer: D

Table that lists the inputs for required change in output state is called
A. Truth table
B. Excitation table
C. State table
D. Clock table
Answer: B

In T flipflop when state of the T flipflop has to be complemented, the T must be
A. 0
B. 1
C. t
D. t+1
Answer: B

A ripple counter's speed is limited by the propagation delay of:
A. Each flip-flop
B. All flip-flops and gates
C. The flip-flops only with gates
D. Only circuit gates
Answer: A

What is the difference between a 7490 and a 7492?
A. 7490 is a MOD-12, 7492 is a MOD-10
B. 7490 is a MOD-12, 7492 is a MOD-16
C. 7490 is a MOD-16, 7492 is a MOD-10
D. 7490 is a MOD-10, 7492 is a MOD-12
Answer: D

How many flip-flops are required to construct a decade counter?
A. 10   
B. 8
C. 5   
D. 4
Answer: D

How many different states does a 3-bit asynchronous counter have?
A. 2   
B. 4
C. 8   
D. 16
Answer: C

Register that shift the information is called
A. Latch
B. Counter
C. Shift register
D. Flipflop
Answer: C

Counters are used to count the:
A. Number of clock pulses
B. Number of glitches
C. Number of flip-flop
D. None of the above
Answer: A